og Layout Engineer

KEY RESPONSIBILITIES:

Implementing layout of digital circuits

DRC LVS and other Physical verification checks

Design Floorplan Routing

Crosstalk Fixes

Electromigration fixes

IR Fixes

Handling different tools: Calibre Virtuoso

PREFERRED EXPERIENCE:

Strong experience with tools for schematics and layout

Versatility with skill scripts and other scripting languages to automate layout flow.

Strong communication skills ability to multitask across projects and work with

geographically spreadout teams

Experience in FinFET & Dual Patterning nodes such as 7/5/3nm

Good understanding of CMOS basics and digital circuits

Strong analytical/problem solving skills and pronounced attention to details.

Requirements

Bachelors degree in Electronics

Minimum of 5 years of Experience in Analog Layout

Perform IC design of FTDI products Perform Verilog RTL design to meet product specifications and requirements Perform front-end verification using UVM methodology Work with Systems and Software engineers on FPGA verification Perform Logic Synthesis, Static Timing Analysis Lead DFT related activities Scan Insertion, ATPG, Pattern Validation Work with Physical designer to achieve timing closure Work with test team in debugging production test issues Help debug & correct any functional issues found in taped-out devices Participate in design reviews, support ISO processes and documentation