AMS Layout Engineer

• As a member of the AMS layout team the candidate will be responsible for delivering fullyverified clean layout this includes the following:
• Designing complex layouts for mixedsignal and analog circuits in CMOS technologies.
• Reviewing and analyzing floorplans and complex circuits with circuit designers.
• Running a complete set of design verification tools available on AMS blocks.
• Interpreting LVS DRC and ERC reports finding the fastest way to complete the layout. Exceeding engineering specifications and expectations by working closely with the circuit design team.
• It utilizes advanced CAD tools and mask design knowledge to deliver correct and robust layouts that meet stringent matching performance area and power requirements.

• Typically requires an experience of 48 years in AMS layout design.
• Good knowledge of electronic devices and semiconductor theory.
• Knowledge of MENTOR GRAPHICS(Calibre) /CADENCE(Virtuoso Assura) layout tools.
• High proficiency in interpreting CALIBRE DRC ERC LVS etc. reports.
• Experience implementing analog layouts to achieve tight matching low noise and low power consumption.
• Layouts may include analog blocks like ADC LDO Charge pumps AMP pad IOs ESD structures etc.
• Must understand techniques for managing IR drop RC delay electromigration and coupling capacitance.
• Must recognize failureprone circuit and layout structures have experience with analog and DFM best practices and proactively work with circuit designers to identify the best approach to solving problems.
• Familiarity with MOS transistor electrical characteristics and CMOS circuit basics is required Strong in Custom Analog Layout design.

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